By S. Takagi (auth.), Dr. Athanasios Dimoulas, Evgeni Gusev, Professor Paul C. McIntyre, Professor Marc Heyns (eds.)
Will nanoelectronic units proceed to scale in line with Moore’s legislation? At this second, there's no effortless solution when you consider that gate scaling is swiftly rising as a significant roadblock for the evolution of CMOS know-how. Channel engineering in response to high-mobility semiconductor fabrics (e.g. strained Si, substitute orientation substrates, Ge or III-V compounds) may possibly aid triumph over the stumbling blocks in view that they give functionality enhancement. There are a number of matters although. can we understand how to make advanced engineered substrates (e.g. Germanium-on-Insulator)? that are the easiest interface passivation methodologies and (high-k) gate dielectrics on Ge and III-V compounds? do we method those fabrics briefly channel transistors utilizing flows, toolsets and know the way just like that during Si expertise? How do those fabrics and units behave on the nanoscale? The reader gets a transparent view of what has been performed up to now, what's the state of the art and that are the most demanding situations forward earlier than we come any as regards to a manageable Ge and III-V MOS technology.
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Extra resources for Advanced Gate Stacks for High-Mobility Semiconductors
It should be noted that most of these techniques tend to produce high strain along a speciﬁc direction (uni-axial strain). Actually, the experimental results of uni-axial strain in Fig. 7 have been obtained from MOSFETs with SiGe source/drain, above described [7, 35–37]. Advantages of the local strain technologies are listed as follows: (1) since the standard CMOS processes can be used with minor changes and novel wafers are not needed, the implementation is easy and the production cost is low; (2) By using uni-axial strain, high performance enhancement of p-channel MOSFETs can be obtained even with comparatively small amount of strain.
1612 (2001) 44. T. Mizuno, N. Sugiyama, T. Tezuka, and S. Takagi, IEEE Trans. Electron Devices 50, p. 988 (2003) 45. W. T. L. -Y. A. A. Fitzgerald, J. Appl. Phys. 92, p. 3745 (2002) 46. R. Oberhuber, G. Zandler and P. Vogl, Phys. Rev. B 58, 9941 (1998) 47. H. Nakatsuji, Y. Kamakura and K. Taniguchi, Int. Electron Devices Meet. Tech. , San Francisco, p. 727 (2002) 48. T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, T. Maeda and S. Takagi, Int. Electron Devices Meet. Tech. , San Francisco, p. 31 (2002) 49.
94, p. 1079 (2003) 51. L. Shifren, X. Wang, P. Matagne, B. Obradovic, C. Auth, S. Cea, T. Ghani, J. He, T. Hoﬀman, R. Kotlyar, Z. Ma, K. Mistry, R. Nagisetty, R. Shaheed, M. Stettler, C. D. Giles: Appl. Phys. 85, p. 6188 (2004) 52. J. L. F. Gibbons, IEEE Electron Device Lett. 15, p. 100 (1994) 53. T. Mizuno, S. Takagi, N. Sugiyama, H. Satake, A. Kurobe, and A. Toriumi, IEEE Electron Device Lett. 21, p. 230 (2000) 54. S. Takagi, T. Mizuno, N. Sugiyama, T. Tezuka and A. Kurobe, IEICE Trans. Electron.
Advanced Gate Stacks for High-Mobility Semiconductors by S. Takagi (auth.), Dr. Athanasios Dimoulas, Evgeni Gusev, Professor Paul C. McIntyre, Professor Marc Heyns (eds.)